IntroductionHello it's a me again drifter1!
After covering FPGA Design using Altera/Intel 's Quartus a few years ago on Steemit, its finally time to get into Xilinx FPGAs as well. I currently own a Spartan-6 Family FPGA and thus I will cover the older software ISE at its latest version 14.7.So, without further ado, let's get straight into it!
What is Xilinx's ISE Design Suite?
The ISE Design Suite is Xilinx's FPGA design environment, that allows you to take a design from design entry to device programming. There are various editions available that are meant for logic, embedded or DSP system designers. In this article, we will be using the System Edition that includes all the tools and capabilities that ISE has to offer.
More specifically, the design flow includes:
- Design creation - create/add HDL source files and other design modules
- Synthesis - compile the design from HDL sources into an architecture-specific design netlist
- Simulation - verify the functionality of the design using simulation
- Constraints - specify design constraints for timing, placement and more
- Implementation - convert logic design into a physical format that can be downloaded to the target device
- Implementation Analysis - analyze the design for performance, device resource utilization, timing and power (static report files)
- Device Configuration and Programming - configure the device and download the files from the host to a Xilinx device/FPGA
How and Where to Download
To be able to download Xilinx's software you have to create a Xilinx account (which might change into AMD account soon, because AMD acquired Xilinx). Lots of personal information will also be requested, like the home address, when you request to download ISE. To create an account or login into an existing one click here .
ISE can be downloaded from Xilinx's webpage. Being the older version (Vivado is the new one), ISE can only be found in the Downloads archive.
- Windows 7/XP/Server and Linux natively (14.7 version)
- Windows 10 through included-VM (14.7 Windows 10)
The Windows 10 installation can become quite problematic and so I suggest you use a Virtual Machine and install the 14.7 version on top of that or dual-boot with some Linux-Distro. I dual-boot Windows 10 and Ubuntu. Don't forget to scroll down to get the full product installation. Spartan-6 and Virtex-6 family FPGAs are supported by all versions, but older families like Spartan-3 might not!
To install ISE on Ubuntu:
- unzip the zipped archive (Xilinx_ISE_DS_14.7_1015_1.tar in my case)
- IMPORTANT: run xsetup with root privileges
Hit Next and accept the licence agreements, until the Select Products to Install section comes up. There you can choose the Logic Edition for the minimal features, or go with the full-on Experience of the System Edition, as I have:
USB JTAG Drivers
To get the drivers up and running for the Digilent USB JTAG Adapter, I used the steps from the YouTube video: How to install Xilinx ISE Design Suite 14.7 on Ubuntu 18.04 (with drivers)
The steps are:
- Install Xilinx Drivers:
- Install Digilent Drivers:
- Install various packages:
sudo apt-get install gitk git-gui libusb-dev build-essential libc6-dev-i386 fxload libftdi-dev
- Install USB Driver:
sudo git clone git://git.zerfleddert.de/usb-driver
sudo make (Use make for both 32-bit and 64-bit)
- To solve "WARNING:iMPACT - Module windrvr6 is not loaded" we write the ffollowing in the terminal from which ISE/IMPACT gets started:
I also suggest "bashing" the settings file:
sudo nano ~/.bashrc
- Add source /opt/Xilinx/14.7/ISE_DS/settings64.sh to the end of the file
- Ctrl+O to save and then Ctrl+X to exit nano
The ISE Project Navigator should pop up:
Get LicenceYou can get a licence from the Licence Solution Center. You simply open the Xilinx.lic file ( that you get from an email from Xilinx) from the Manage Licence Window that pops up the first time you open ISE or from Help/Manage License... in the Toolbar.
Full-On ExampleLet's go through the steps of designing a simple complete FPGA Design.
Project Set-UpWhile in the ISE Project Navigator on the left side are Project commands, one of which is called New Project. Clicking on that option the New Project Wizard should come forth:
There we can define the name, location, directory, description and top-level source type. After hitting Next, the Project Settings come up, where we define more specific device and project properties. I have an ALINX AX309 Spartan-6 FPGA Development Board (boards are widely available on Ebay - I bought mine from Ebay as well) and we will be coding in VHDL, therefore I have to insert the following information:
The Device Properties can be changed later on (for example to program a different device) by right clicking on the Hierarchy and choosing the Design Properties option from the drop-down menu:
Let's now write some VHDL code.
My FPGA has a total of 6 buttons that I can press, and 4 LEDs and a six-digit seven-segment display to output too, that we can play with. Let's use 2 buttons and 1 led to output the result of a XOR gate, for the purpose of this article.
Right-Clicking on the Hierarchy and choosing the New Source option the New Source Wizard comes up, where we will choose to create a VHDL Module with the name xor2_gate:
After hitting next we got to Define Module, where we can define the input and output ports for the module:
Double-clicking the xor2_gate component from the Hierarchy, we will see that the following VHDL code has been pre-generated (I like to remove the comments):
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity xor2_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end xor2_gate;
architecture Behavioral of xor2_gate is
We simply have to add
C <= A xor B;after the begin "statement" of the architecture, to get the behavior that we want.
Constraints File (Pin Assignment)
Starting another New Source Wizard we choose Implementation Constraints File (UCF) and give the name xor2_constraints :
Based on the schematics of my board, KEY1 is connected to FPGA pin C3, KEY2 to D3 and LED0 to P4.
The generic form of an port assignment constraint is:
Thus, the .ucf file for our design is:
NET "signal_name" LOC = "fpga_pin" ;
NET "A" LOC = "C3" ; NET "B" LOC = "D3" ; NET "C" LOC = "P4" ;
SynthesisHaving the source file xor2_gate selected, below the Hiearchy, we double click on Synthesize - XST. If no error occurs their should be a green tick to the left of that option, and the Design Summary on the right should become updated:
As we can see 1 LUT slice out of the 5720 available has been utilized (for the xor gate), as well as 3 IOB's have been bound for the corresponding 2 input pins and 1 output pin. There are no errors or warnings.
ImplementationIn the same way, double-clicking on Implement Design the design gets implemented for the specific FPGA that I chose giving us a more advanced Design Utilization Summary:
Device ProgrammingLastly, let's generate the programming file by double-clicking on Generate Programming File.
To program the FPGA we have to open up IMPACT from Configure Target Device:
Scanning for devices, my device shows up:
And Right-Clicking and hitting Program on the FPGA we see the following behavior:
Voila! A XOR Gate.
If you followed this steps you should now have successfuly programmed your first FPGA!
Final Words | Next Up
And this is actually it for today's post! Thank you for your time!
Now that we started getting into Xilinx FPGAs be sure that even more content around that will come soon! Maybe even Xilinx's Vivado software, but I don't own a newer board yet, so that might take a while...
Keep on Drifting!