Logic Design - Circuit Examples in SystemVerilog

in STEMGeeks10 months ago

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Hey it's a me again @drifter1!

Today we continue with the Logic Design series on SystemVerilog in order to get into Circuit Examples. Both combinational and sequential logic will be covered!

So, without further ado, let's get straight into it!

Combinational Logic

In Verilog and SystemVerilog combinational circuitry can be written using:

  • assign statement (data flow representation)
  • combinational always block
  • gate primitives (structural representation)
  • user-defined primitives (truth table)

The main difference between SystemVerilog and Verilog is that a combinational always block uses a different keyword, always_comb, instead of always, so that unintentional design mistakes are avoided.

Let's only cover such implementations...


The best way of implementing encoders, decoders and multiplexers in SystemVerilog is within a combinational always block, and using either if-else statements or a case statement. The second approach usually leads to better maintainability.

Let's, for example, consider an 4-to-2 encoder with input i and output o. One valid implementation in SystemVerilog looks like this:

module encoder_4to2 (output [1 : 0] o, input [3 : 0] i);
        case (i)
            4'b0001 : o = 2'b00;
            4'b0010 : o = 2'b01;
            4'b0100 : o = 2'b10;
            4'b1000 : o = 2'b11;
            default : o = 2'bxx;

Sequential Logic

Sequential logic in Verilog and SystemVerilog is written within sequential always blocks. This includes Flips Flops, Latches and Counters. The main difference of SystemVerilog and Verilog is that different keywords are used instead of a simple always. There are two keywords of them, one for flip flops and one for latches, which are always_ff and always_latch respectively.

Flip Flops

Specifying a synchronous reset D-FF in SystemVerilog looks like this:

module dff (output reg q, input d, clk, reset);
    always_ff @ (posedge clk) begin
        if (~reset)
            q <= 1'b0;
            q <= d;


A simple D-Latch with enable and reset looks like this:

module dlatch (output reg q, input d, reset, en);
        if (~reset)
            q <= 1'b0;
        else if (en)
            q <= d;

In Verilog, such non-synthesizable circuitry is sometimes accidentally generated due to the use of the same keyword, always, for all types of blocks. So, these specialized blocks are a big plus for SystemVerilog!



  1. https://www.chipverify.com/systemverilog/systemverilog-tutorial
  2. https://www.asic-world.com/systemverilog/tutorial.html


  1. https://www.flickr.com/photos/creative_stock/5227842611

Block diagrams and other visualizations were made using draw.io

Previous articles of the series



  • From Verilog To SystemVerilog → Data Types, Arrays, Structures, Operators and Expressions
  • Control Flow → Additional Procedural Blocks, Loops, Conditional Statements, Functions and Task Features
  • Processes → Fork - Join in Verilog and SystemVerilog, Process Control (wait fork, disable fork)
  • Events → Interprocess Communication, Events (Definition, Triggering, Waiting, Sequencing, Merging, as Arguments)
  • Semaphores and Mailboxes → Semaphores (Creation, Methods), Mailboxes (Definition, Methods)
  • Interfaces (part 1) → Interfaces (Definition, Port and Signal Lists, Instantiation), Modports
  • Interfaces (part 2) → Parameters, Tasks and Functions (Importing, Exporting), Clocking Blocks (Input and Output Skews)
  • Classes (part 1) → Classes (Definition, Constructor Function, Creating Objects, Accessing Class Members, Static and Constant Class Members, Arrays)
  • Classes (part 2) → Copying Objects (Shallow and Deep Copy), Inheritance, Polymorphism, Virtual Methods
  • Classes (part 3) → Parameterized Classes, Out-of-Block Method Declaration, Data Accessibility, Abstract / Virtual Classes
  • Program Blocks → Design and Testbench, Program Block (Reactive Region, Allowed Constructs)
  • Packages → Design Hierarchy, Packages (Definition, Importing, Definition Collision)
  • Constraints and Randomization → Testing and Verification, Random Variables (Standard, Random-Cyclic), Randomize Method (Constraint and Random Mode, Pre / Post Randomize)
  • Constraint Blocks → Constraint Blocks (Syntax, Rules), External (Explicit, Implicit), Static, Soft and In-Line Constraints
  • Constraint Types (part 1) → Simple Expressions, Set Membership (Inside Operator, Range, Set, Inverted), Weighted Distributions (Dist Operator, := and :/)
  • Constraint Types (part 2) → Conditional Relations (Implication Operator, If-Else), Iterative Constraints, Solve - Before, Random Case
  • Functional Coverage → Functional Coverage (Limitations, Types), Covergroups (Sampling, Coverage Points, Coverpoint Bins, Conditional Coverage, Cross Coverage, Coverage Options)
  • Assertions → Assertions, Immediate Assertions, Concurrent Assertions (Boolean, Sequence, Property, Assert), Assume, Cover and Expect
  • Command Line Arguments and Dynamic Casting → Command Line Arguments (Passing, Using), Dynamic Casting

Final words | Next up

And this is actually it for today's post!

See Ya!

Keep on drifting!

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