The OR logic gate includes an AND gate which is always high, true and passing a consistent value of 1. AND is constant and equal to 1, the EI (either) gate becomes active.

There is a mathematical masking, when EI is false (0) the always affirmative AND is masked by multiplication (AND in series with EI) which allows the pseudo-false state to exist by mathematical operation.

The product of AND * EI can be resolved in two cases for OR. Where EI = 0 (false), (1 * 0 = 0) ..OR receives the value zero. In the affirmative case OR receives a value of 1 from it's helpers (1 * 1 = 1). ORomeo seems quite the romantic with AND EI producing positive value for him.

Patching the ENIAC from WWII.

A vintage 1945 ORomeo bug, logged in 2019.

Sketched over newspaper, an EI (either) logic circuit.

For two semiconductor channels (transistors) the circuit designed performs the necessary logic.

When either of two switches is on (1), the output should be 1 (light on).

When both switches are on (1), the output should be 0 (light off).

The EI (either) logic circuit functions correctly in the chosen configuration, on paper.

The OR logic limitation expresses itself clearly with two switches and an electric light-source.

With an OR circuit, when both switches are on (1), the output is 1 (light on).

The EI operator provides a true EXCEPTION (either) logic gate. The pseudo-exclusion provided by OR no longer needs to mathematically emulate the EI (either) logic.

Can a prototype be etched?

Even with quantum computation in development, I can see the benefit of correcting logical operators which rely on mathematical operation rather than circuitry. Many existing logical operators have their roots in a time before transistors when digital architecture needed to be expressed using the technologies which were available at the time (relays and vacuum tubes).